Semiconducotr memory device including non-volatile memory cell array

ABSTRACT

A semiconductor memory device that may correct error data using an error correction circuit is disclosed. The semiconductor memory device may include a DRAM cell array, a parity generator, a nonvolatile memory cell array and an error correction circuit. The parity generator is configured to generate a first set of parity bits having at least one bit based on input data. The nonvolatile memory cell array may store the input data and the first set of parity bits corresponding to the input data, and to output first data corresponding to the input data, and a second set of parity bits corresponding to the first set of parity bits. The error correction circuit is configured to generate second data as corrected data based on the first data.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to Korean PatentApplication No. 10-2013-0012407 filed on Feb. 4, 2013, the entirecontents of which are incorporated herein by reference in theirentirety.

BACKGROUND

Embodiments of the disclosure relate to a semiconductor memory device,and particularly, to a semiconductor memory device including anon-volatile memory cell array that corrects errors using an errorcorrection circuit.

Recently, a semiconductor memory device including a non-volatile memorycell array in a dynamic random access memory (DRAM) device has beenstudied. The non-volatile memory cell array may include an anti-fusecell array that is used to activate a redundancy cell array whendefective cells are included in a memory cell array. However, it isdesirable to reduce an area of the anti-fuse cell array to improve aproductivity of the semiconductor memory device.

SUMMARY

Embodiments of the disclosure provide a semiconductor memory deviceincluding a non-volatile memory cell array that occupies small area of asemiconductor chip.

The technical objectives of the inventive concept are not limited to theabove disclosure; other objectives may become apparent to those ofordinary skill in the art based on the following descriptions.

In accordance with an exemplary embodiment, a semiconductor memorydevice includes a dynamic random access memory (DRAM) cell array, aparity bit generator, a nonvolatile memory cell array and an errorcorrection circuit.

The parity bit generator is configured to generate a first set of paritybits having at least one bit based on input data received from outsidethe semiconductor memory device. The nonvolatile memory cell array isconfigured to store the input data and the first set of parity bitscorresponding to the input data, and to output first data correspondingto the input data and a second set of parity bits corresponding to thefirst set of parity bits. The error correction circuit is configured togenerate second data as corrected data based on the first data and thesecond set of parity bits. The semiconductor memory device is configuredto use the second data to select a spare cell of the DRAM cell array.

In an embodiment, the semiconductor memory device is configured to usethe second data as corrected data if the first data is different fromthe input data.

In another embodiment, the semiconductor memory device is configured touse the second data to replace a defective word line of the DRAM cellarray with a spare word line.

In still another embodiment, the semiconductor memory device isconfigured to use the second data to replace a defective columnselecting line of the DRAM cell array with a spare column selectingline.

In yet another embodiment, the DRAM cell array may include a normalmemory cell array connected to word lines and column selecting lines,and a spare memory cell array connected to spare word lines and sparecolumn selecting lines.

In yet another embodiment, the semiconductor memory device may furtherinclude a column decoder and a spare column decoder.

The column decoder is configured to generate column selection signalsand to provide the column selection signals to the column selectinglines. The spare column decoder is configured to generate spare columnselection signals based on the second data, and to provide the sparecolumn selection signals to the spare column selecting lines when adefective cell is included in the normal memory cell array.

In yet another embodiment, the second data may be anti-fuse programdata.

In yet another embodiment, the semiconductor memory device may be astacked memory device in which a plurality of chips communicating dataand control signals through a through-silicon-via (TSV) are stacked.

In yet another embodiment, the nonvolatile memory cell array may includean anti-fuse cell array having a plurality of anti-fuse cells.

In yet another embodiment, a number of bits of the first set of paritybits is smaller than a number of bits of the input data.

In accordance with another exemplary embodiment, a semiconductor memorydevice includes a DRAM cell array, a nonvolatile memory cell array andan error correction circuit.

The nonvolatile memory cell array is configured to store input data anda first set of parity bits having at least one bit, the input data andthe first set of parity bits received from outside the semiconductormemory device. The error correction circuit is configured to generatesecond data as corrected data based on first data corresponding to theinput data, the first data being received from the nonvolatile memorycell array, and a second set of parity bits corresponding to the firstset of parity bits, the second set of parity bits being received fromthe nonvolatile memory cell array. The semiconductor memory device isconfigured to use the second data to repair a defective cell included inthe DRAM cell array.

In an embodiment, the semiconductor memory device may be suitable forrepairing defective bits in a semiconductor wafer level beforepackaging.

According to embodiments of the disclosure, a semiconductor memorydevice including a non-volatile memory cell array may correct error bitsusing an error correction circuit. Therefore, the semiconductor memorydevice may have a small chip size.

In accordance with an exemplary embodiment, a semiconductor memorydevice includes a memory cell array, a parity bit generator, ananti-fuse cell array and an error correction circuit.

The parity bit generator is configured to generate a first set of paritybits having at least one bit based on first data received from outsidethe semiconductor memory device. The anti-fuse cell array includes aplurality of anti-fuse cells configured to store the first data and thefirst set of parity bits, and to transfer second data corresponding tothe first data, and a second set of parity bits corresponding to thefirst set of parity bits. The error correction circuit is configured togenerate third data as corrected data based on the second data and thesecond set of parity bits. The semiconductor memory device is configuredto use the third data to select a spare cell of the memory cell array.

BRIEF DESCRIPTION OF THE DRAWINGS

Illustrative, non-limiting example embodiments will be more clearlyunderstood from the following detailed description taken in conjunctionwith the accompanying drawings. In the drawings:

FIG. 1 is an exemplary block diagram illustrating a semiconductor memorydevice including a non-volatile memory cell array, in accordance with anembodiment;

FIG. 2 is an exemplary table illustrating an array area increaseaccording to parity bits when error correction is performed usingHamming codes, in accordance with an embodiment;

FIG. 3 is a diagram illustrating an example of the Hamming codes used inFIG. 2;

FIG. 4 is an exemplary block diagram illustrating a semiconductor memorydevice including a non-volatile memory cell array, in accordance withanother embodiment;

FIG. 5 is a circuit diagram illustrating the non-volatile memory cellarray in FIG. 1, in accordance with an embodiment;

FIG. 6 is a block diagram illustrating a semiconductor memory deviceincluding a non-volatile memory cell array, in accordance with stillanother embodiment;

FIG. 7 is a perspective view of an example of a stacked semiconductordevice including one or more semiconductor memory devices in accordancewith certain embodiments;

FIG. 8 is a diagram of an example of a memory system including asemiconductor memory device in accordance with certain embodiments;

FIG. 9 is a block diagram of another example of a memory systemincluding a semiconductor memory device in accordance with certainembodiments; and

FIG. 10 is a block diagram of an example of an electronic systemincluding a semiconductor memory device in accordance with certainembodiments.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Example embodiments of the present disclosure will be described morefully with reference to the accompanying drawings, in which some exampleembodiments are shown. The present disclosure may, however, be embodiedin many different forms and should not be construed as limited to theembodiments set forth herein. Like reference numerals refer to likeelements throughout the accompanying drawings.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements. Other words used to describe relationships betweenelements should be interpreted in a like fashion (i.e., “between” versus“directly between,” “adjacent” versus “directly adjacent,” etc.).

It will be understood that, although the terms first, second, A, B, etc.may be used herein in reference to elements of the disclosure, suchelements should not be construed as limited by these terms. Unlessindicated otherwise, these terms are used to distinguish one elementfrom another. For example, a first element could be termed a secondelement, and a second element could be termed a first element, withoutdeparting from the scope of the present disclosure. Herein, the term“and/or” includes any and all combinations of one or more referents.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element's or feature's relationship to another element(s)or feature(s) as illustrated in the figures. It will be understood thatthe spatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the term “below” can encompass both an orientation ofabove and below. The device may be otherwise oriented (rotated 90degrees or at other orientations) and the spatially relative descriptorsused herein interpreted accordingly.

The terminology used herein to describe embodiments of the invention isnot intended to limit the scope of the invention. The articles “a,”“an,” and “the” are singular in that they have a single referent,however the use of the singular form in the present disclosure shouldnot preclude the presence of more than one referent. In other words,elements of the disclosure referred to in the singular may number one ormore, unless the context clearly indicates otherwise. It will be furtherunderstood that the terms such as “comprises,” “comprising,” “includes,”and/or “including,” when used herein, specify the presence of statedfeatures, items, steps, operations, elements, and/or components, but donot preclude the presence or addition of one or more other features,items, steps, operations, elements, components, and/or groups thereof.

Embodiments are described herein with reference to cross-sectionalillustrations that are schematic illustrations of idealized embodiments(and intermediate structures). As such, variations from the shapes ofthe illustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, embodiments should not beconstrued as limited to the particular shapes of regions illustratedherein but are to include deviations in shapes that result, for example,from manufacturing. For example, an implanted region illustrated as arectangle will, typically, have rounded or curved features and/or agradient of implant concentration at its edges rather than a binarychange from implanted to non-implanted region. Likewise, a buried regionformed by implantation may result in some implantation in the regionbetween the buried region and the surface through which the implantationtakes place. Thus, the regions illustrated in the figures are schematicin nature and their shapes are not intended to illustrate the actualshape of a region of a device and are not intended to limit the scope ofthe present inventive concept.

Unless otherwise defined, all terms (including technical and scientificterms) used herein are to be interpreted as is customary in the art towhich this disclosure belongs. It will be further understood that termsin common usage should also be interpreted as is customary in therelevant art and not in an idealized or overly formal sense unlessexpressly so defined herein.

FIG. 1 is an exemplary block diagram illustrating a semiconductor memorydevice 100 including a non-volatile memory cell array, in accordancewith an embodiment.

Referring to FIG. 1, the semiconductor memory device 100 may include aDRAM cell array 110, a parity bit generator 130, a nonvolatile memorycell array 120 and an error correction circuit 140.

The parity bit generator 130 may generate a first set of parity bitshaving at least one bit based on input data DIN_NVM. The nonvolatilememory cell array 120 may store the input data DIN_NVM and the first setof parity bits, and output first data corresponding to the input dataDIN_NVM and a second set of parity bits corresponding to the first setof parity bits. The error correction circuit 140 generates error databased on the first data and the second set of parity bits received fromthe nonvolatile memory cell array 120, respectively, to correct thefirst data based on the error data, and generate second data DOUT_NVM.

The second data DOUT_NVM may be used to repair a defective cell includedin the DRAM cell array 110. The second data DOUT_NVM may be used toreplace a defective word line of the DRAM cell array with a spare wordline. The second data DOUT_NVM may be used to replace a defective columnselecting line of the DRAM cell array with a spare column selectingline.

According to an embodiment, the DRAM cell array 110 may include a normalmemory cell array connected to word lines and column selecting lines,and a spare memory cell array connected to spare word lines and sparecolumn selecting lines.

According to an embodiment, the semiconductor memory device 100 mayfurther include a column decoder and a spare column decoder. The columndecoder may decode column address signals to generate column selectionsignals, and provide the column selection signals to the columnselecting lines. The spare column decoder may generate spare columnselection signals based on the second data, and provide the spare columnselection signals to the spare column selecting lines when a defect isgenerated in at least one column selecting line of the column selectinglines.

The second data DOUT_NVM may be anti-fuse program data. The nonvolatilememory cell array 120 may include an anti-fuse cell array. Thesemiconductor memory device 100 may be suitable for repairing defectivebits in a system level.

FIG. 2 is an exemplary table illustrating an array area increaseaccording to parity bits when error correction is performed usingHamming codes, in accordance with an embodiment.

Referring to FIG. 2, it shows that an array area overhead, that is, anarea occupied by an error correction circuit in a semiconductor wafer,is reduced according as the number of data bits and parity bitsincrease. For example, when the number of data bits is 16 and the numberof parity bits is 5, it shows that a code word may have 21 bits and thearray area overhead 31.3%.

FIG. 3 is a diagram illustrating an example of the Hamming codes used inFIG. 2. In FIG. 3, Hamming codes are shown when the number of data bitsis 16, and the number of parity bits is 5. The data bits have 16 bitsfrom 0 to 15, the parity bits have 5 bits from P0 to P4, and the codeword has 21 bits.

Since the semiconductor memory device according to disclosed embodimentscorrect errors of data stored in the non-volatile memory cell using theerror correction circuit 140, the semiconductor memory device accordingto disclosed embodiments may occupy a semiconductor chip area smallerthan the conventional semiconductor memory device.

In the conventional art, a semiconductor memory device may include amain cell and a voting cell having the same structure as the main cellto reduce error of data stored in the non-volatile memory cell. In thiscase, the semiconductor memory device may occupy double the areacompared to a non-volatile memory cell including only a main cell.

FIG. 4 is an exemplary block diagram illustrating a semiconductor memorydevice 200 including a non-volatile memory cell array, in accordancewith another embodiment.

Referring to FIG. 4, the semiconductor memory device 200 may include aDRAM cell array 110, a nonvolatile memory cell array 120 a, and an errorcorrection circuit 140.

The nonvolatile memory cell array 120 a may store the input data DIN_NVMand a first set of parity bits PAR having at least one bit received fromthe exterior. The input data DIN_NVM and the first set of parity bitsPAR are provided from outside the semiconductor memory device 200. Thenonvolatile memory cell array 120 a may store the input data DIN_NVM andthe first set of parity bits PAR, and output first data corresponding tothe input data DIN_NVM and a second set of parity bits corresponding tothe first set of parity bits PAR. The error correction circuit 140 maygenerate error data based on the first data and the second set of paritybits, to correct the first data based on the error data, and generatesecond data DOUT_NVM.

In the semiconductor memory device 200 of FIG. 4, parity bits related tothe input data DIN_NVM may be input from outside the semiconductormemory device 200. Therefore, in this example, the semiconductor memorydevice 200 does not include a parity generator, unlike the semiconductormemory device 100 of FIG. 1.

An operation of the semiconductor memory device 200 of FIG. 4 may besimilar to that of the semiconductor memory device 100 of FIG. 1. Thesemiconductor memory device 200 of FIG. 4 may be suitable for repairingdefective bits in a semiconductor wafer level before packaging.

FIG. 5 is a circuit diagram illustrating the non-volatile memory cellarray in FIG. 1 and FIG. 4, in accordance with an embodiment. In FIG. 5,an anti-fuse cell array is shown as an example of non-volatile memorycell array.

Referring to FIG. 5, an anti-fuse cell array 122 may include anti-fusecells A1_1 to A256_1 and selection transistors MN1_1 to MN256_1connected in series to the anti-fuse cells A1_1 to A256_1. Also, theanti-fuse cell array 122 may include anti-fuse cells A1_2 to A256_2 andselection transistors MN1_2 to MN256_2 connected in series to theanti-fuse cells A1_2 to A256_2.

In one embodiment, an anti-fusing voltage VANT1 may be applied to gatesof the respective anti-fuse cells A1_1 to A256_1, and sources of therespective anti-fuse cells A1_1 to A256_1 may be floated. The selectiontransistors MN1_1 to MN256_1 may have drains, which are electricallyconnected to drains of the anti-fuse cells A1_1 to A256_1, respectively,and gates to which a word line drive signal WL1 is applied. Sources ofthe selection transistors MN1_1 to MN256_1 may be electrically connectedto bit lines BL1 to BL256, respectively.

An anti-fuse voltage VANT2 may be applied to gates of the respectiveanti-fuse cells A1_2 to A256_2, and sources of the respective anti-fusecells A1_2 to A256_2 may be floated. The selection transistors MN1_2 toMN256_2 may have drains, which are electrically connected to drains ofthe anti-fuse cells A1_2 to A256_2, respectively, and gates to which aword line drive signal WL2 is applied. Sources of the selectiontransistors MN1_2 to MN256_2 may be electrically connected to the bitlines BL1 to BL256, respectively.

Hereinafter, an exemplary operation of the anti-fuse cell array 122 ofFIG. 5 will be described.

When the anti-fuse cell A1_1 is programmed, a high voltage of, forexample, about 6 V may be applied as an anti-fusing voltage VANT1 to thegates of the anti-fuse cells A1_1 to A256_1. A voltage VANT1/2 of, forexample, about 3 V may be applied to the gate of the selectiontransistor MN1_1 connected to the drain of the anti-fuse cell A1_1 toturn on the selection transistor MN1_1. A low electric potential of, forexample, about 0 V may be applied to the bit line BL1 electricallyconnected to the source of the selection transistor MN1_1. Under thiscondition, a thin gate oxide layer of the anti-fuse cell A1_1 may bebroken to form an ohmic contact between a gate electrode and the drain.Thus, a current path may be formed from a gate electrode of theanti-fuse cell A1_1 to the bit line BL1. In this case, a voltage VANT1/2of, for example, about 3 V may be applied to bit lines (e.g., BL2 toBL256) electrically connected to unselected cells so that a high voltageis not applied to both ends of the gate oxide layer of the respectiveanti-fuse cells A2_1 to A256_1. Also, a low voltage of, for example,about 0 V may be applied to gates of the anti-fuse cells A1_2 to A256_2to be unprogrammed and gates of the selection transistors MN1_2 toMN256_2 so that unselected anti-fuse cells may not be programmed.

FIG. 6 is a block diagram illustrating a semiconductor memory device 300including a non-volatile memory cell array, in accordance with stillanother embodiment. In FIG. 6, an embodiment of a method of repairing adefective cell included in the DRAM cell array using the second dataDOUT_NVM in which error is corrected is illustrated. The second dataDOUT_NVM may be output from the error correction circuit of thesemiconductor memory device 100 of FIG. 1. Also, the second dataDOUT_NVM may be output from the error correction circuit of thesemiconductor memory device 200 of FIG. 4. The second data DOUT_NVM maybe anti-fuse program data.

Referring to FIG. 6, the semiconductor memory device 300 may include afirst register 320 that stores the second data DOUT_NVM, and second andthird registers 332 and 334 that store the anti-fuse program datareceived from the first register 320. Further, the semiconductor memorydevice 300 may include a memory cell array 340 that stores data, a rowdecoder and a column decoder 352 and 354 that drive word lines and bitlines of the memory cell array 340, a spare row decoder and a sparecolumn decoder 362 and 364 that drive spare cells, and a row comparatorand a column comparator 372 and 374 that compare address information ofa defective cell and external address information.

The first register 320 stores the anti-fuse program data (the seconddata DOUT_NVM), and then transfers the anti-fuse program data to thesecond and the third registers 332 and 334. Operation conditions of asemiconductor memory device 300 may be set using the anti-fuse programdata stored in the second and the third registers 332 and 334.

The second and the third registers 332 and 334 may sequentially receiveand store one-by-one bit of the anti-fuse program data from the firstregister 320. The second and the third registers 332 and 334 may bearranged adjacent to various circuit blocks requiring the anti-fuseprogram data. For example, the second register 332 that stores the rowaddress information of a defective cell may be arranged adjacent to therow comparator 372. Further, the third register 334 that stores thecolumn address information of a defective cell may be arranged adjacentto the column comparator 374.

The row comparator 372 compares the row address received from theexterior with the row address information of a defective cell, anddrives the row decoder 352 or the spare row decoder 362 according to thecomparison result. Similarly, the column comparator 374 compares thecolumn address received from the exterior with the column addressinformation of a defective cell, and drives the column decoder 354 orthe spare column decoder 364 according to the comparison result.

The row comparator 372 and the column comparator 374 may include aplurality of logic devices to compare the address information receivedfrom the exterior and the address information of the defective cell,respectively.

FIG. 7 is a perspective view of an example of a stacked semiconductordevice 400 including one or more semiconductor memory devices inaccordance with certain embodiments.

Referring to FIG. 7, the stacked semiconductor device 400 may include aninterface chip 410, and memory chips 420, 430, 440 and 450 which areelectrically connected through through-substrate vias (e.g.,through-silicon vias) 460. Although the through-substrate vias 460disposed in two rows are shown in FIG. 7, the stack semiconductor device400 may include any number of through-substrate vias.

The memory chips 420, 430, 440 and 450 included in the stackedsemiconductor device 400 may correct error data of a non-volatile memorycell array using the error correction circuit according to the disclosedembodiments. The interface chip 410 may perform as an interface betweenthe memory chips 420, 430, 440 and 450 and an external device.

FIG. 8 is a diagram of an example of a memory system 500 including asemiconductor memory device in accordance with certain embodiments.

Referring to FIG. 8, the memory system 500 may include a motherboard531, a chip set (or a controller) 540, slots 535_1 and 535_2, memorymodules 550 and 560, and transmission lines 533 and 534. Buses 537 and539 may connect the chip set 540 with the slots 535_1 and 535_2. Aterminal resistor Rtm may terminate each of the buses 537 and 539 on aPCB of the motherboard 531.

For convenience, in FIG. 8, only two slots 535_1 and 535_2 and twomemory modules 550 and 560 are shown. However, the memory system 500 mayinclude an arbitrary number of slots and memory modules.

The chip set 540 may be mounted on the PCB of the motherboard 531, andcontrol an operation of the memory system 500. The chip set 540 mayinclude connectors 541_1 and 541_2 and converters 543_1 and 543_2.

The converter 543_1 may receive parallel data generated by the chip set540, convert the parallel data to serial data, and output the serialdata to the transmission line 533 via the connector 541_1. The converter543_1 may receive serial data from the memory module 550 via thetransmission line 533, convert the serial data to parallel data, andoutput the parallel data to the chip set 540.

The converter 543_2 may receive parallel data generated by the chip set540, convert the parallel data to serial data, and output the serialdata to the transmission line 534 via the connector 541_2. The converter543_2 may receive serial data from the memory module 560 via thetransmission line 534, convert the serial data to parallel data, andoutput the parallel data to the chip set 540. The transmission lines 533and 534 included in the memory system 500 may be a plurality of opticalfibers.

The memory module 550 may include a plurality of memory devices 555_1 to555_n, a first connector 557, a second connector 551, and a converter553. The memory module 560 may include a plurality of memory devices565_1 to 565_n, a first connector 557′, a second connector 551′, and aconverter 553′.

The first connector 557 may transfer low-speed signals received from thechip set 540 to the memory devices 555_1 to 555_n, and the secondconnector 551 may be connected to the transmission line 533 fortransferring high-speed signals.

The converter 553 may receive serial data via the second connector 551,convert the serial data to parallel data, and output the parallel datato the memory devices 555_1 to 555_n. Further, the converter 553 mayreceive parallel data from the memory devices 555_1 to 555_n, convertthe parallel data to serial data, and output the serial data to thesecond connector 551.

Each of the memory devices 555_1 to 555_n and 565_1 to 565_n may includea semiconductor memory device according to the disclosed embodiments.Therefore, the memory devices 555_1 to 555_n and 565_1 to 565_n maycorrect errors of data stored in a non-volatile memory cell array usingthe error correction circuit according to the disclosed embodiments. Thememory devices 555_1 to 555_n and 565_1 to 565_n may be a volatilememory chip such as a dynamic random access memory (DRAM) and a staticrandom access memory (SRAM), a non-volatile memory chip such as a flashmemory, a phase change memory, a magnetic random access memory (MRAM),or a resistive random access memory (RRAM), or a combination of thereof.

FIG. 9 is a block diagram of another example of a memory system 600including a semiconductor memory device in accordance with certainembodiments.

Referring to FIG. 9, the memory system 600 may include a memorycontroller 610 and a semiconductor memory device 620.

The memory controller 610 may generate address signals ADD and commandsignals CMD, and provide the address signals ADD and the command signalsCMD to the semiconductor memory device 620 through buses. Data DQ may betransmitted from the memory controller 610 to the semiconductor memorydevice 620 through the buses, or transmitted from the semiconductormemory device 620 to the memory controller 610 through the buses.

The semiconductor memory device 620 may correct error of data stored ina non-volatile memory cell array using the error correction circuitaccording to the disclosed embodiments.

FIG. 10 is a block diagram of an example of an electronic system 700including a semiconductor memory device in accordance with certainembodiments.

Referring to FIG. 10, the electronic system 700 in accordance withcertain embodiments may include a central processing unit (CPU) 720electrically connected to a system bus 760, a random access memory (RAM)730, a user interface 740, a MODEM 750 such as a baseband chipset, and anon-volatile memory device (NVM) 710.

The NVM 710 and the RAM 730 may store or output data, and includevarious logic circuits therein. When the electronic system 700 accordingto example embodiments is a mobile device, a battery (not shown) thatsupplies operating voltage to the electronic system 700 may beadditionally provided. Although not shown in FIG. 10, the electronicsystem 700 may be further provided with an application chipset, a cameraimage processor, and a mobile DRAM, that is obvious to an ordinary skillin the art. For example, the NVM 710, may be included in a solid statedrive/disk (SSD) using non-volatile memory devices for storing data.Further, the NVM 710 may be provided as a fusion flash memory in which astatic random access memory (SRAM), a NAND flash memory and a NORinterface logic are combined.

A semiconductor device according to example embodiments may be appliedto a part of the electronic system 700. For example, when the electronicsystem 700 is booting, the example embodiments may be applied in settingoperation environments of the NVM 710 or the RAM 730. Each of the NVM710 and the RAM 730 may include a non-volatile memory cell arrayaccording to the above disclosed embodiments, read information stored inthe non-volatile memory cell array during an initial boosting of the NVM710 or the RAM 730, and use fuse data read from the non-volatile memorycell array as information for setting the operation conditions.

The semiconductor device and/or the system according to exampleembodiments of the inventive concepts may be mounted using various typesof packages. For example, the semiconductor device and/or the system maybe mounted using packages such as a Package on Package (POP), a Ballgrid arrays (BGAs), a Chip scale packages (CSPs), a Plastic Leaded ChipCarrier (PLCC), a Plastic Dual In-Line Package (PDIP), a Die in WafflePack, a Die in Wafer Form, a Chip On Board (COB), a Ceramic Dual In-LinePackage (CERDIP), a Plastic Metric Quad Flat Pack (MQFP), a Thin QuadFlatpack (TQFP), a Small Outline Integrated Circuit (SOIC), a ShrinkSmall Outline Package (SSOP), a Thin Small Outline Package (TSOP), aThin Quad Flatpack (TQFP), a System In Package (SIP), a Multi ChipPackage (MCP), a Wafer-level Fabricated Package (WFP), and a Wafer-LevelProcessed Stack Package (WSP).

The disclosed embodiments may be applied to devices such as asemiconductor device, and particularly, to a semiconductor memory deviceand a memory system including the semiconductor memory device.

The foregoing is illustrative of embodiments and is not to be construedas limiting thereof. Although a few embodiments have been described,those skilled in the art will readily appreciate that many modificationsare possible without materially departing from the novel teachings andadvantages. Accordingly, all such modifications are intended to beincluded within the scope of the present disclosure as defined in theclaims. In the claims, means-plus-function clauses are intended to coverthe structures described herein as performing the recited function, andnot only structural equivalents but also equivalent structures.

What is claimed is:
 1. A semiconductor memory device, comprising: adynamic random access memory (DRAM) cell array; a parity bit generatorconfigured to generate a first set of parity bits having at least onebit based on input data received from outside the semiconductor memorydevice; a nonvolatile memory cell array configured to store the inputdata and the first set of parity bits corresponding to the input data,and to output first data corresponding to the input data and a secondset of parity bits corresponding to the first set of parity bits; and anerror correction circuit configured to generate second data as correcteddata based on the first data and the second set of parity bits, whereinthe semiconductor memory device is configured to use the second data toselect a spare cell included in the DRAM cell array.
 2. The deviceaccording to claim 1, wherein the semiconductor memory device isconfigured to use the second data as corrected data if the first data isdifferent from the input data.
 3. The device according to claim 1,wherein the semiconductor memory device is configured to use the seconddata to replace a defective word line of the DRAM cell array with aspare word line.
 4. The device according to claim 1, wherein thesemiconductor memory device is configured to use the second data toreplace a defective column selecting line of the DRAM cell array with aspare column selecting line.
 5. The device according to claim 1, whereinthe DRAM cell array includes a normal memory cell array connected toword lines and column selecting lines, and a spare memory cell arrayconnected to spare word lines and spare column selecting lines.
 6. Thedevice according to claim 5, further comprising: a column decoderconfigured to generate column selection signals, and to provide thecolumn selection signals to the column selecting lines; and a sparecolumn decoder configured to generate spare column selection signalsbased on the second data, and to provide the spare column selectionsignals to the spare column selecting lines when a defective cell isincluded in the normal memory cell array.
 7. The device according toclaim 1, wherein the second data is anti-fuse program data.
 8. Thedevice according to claim 1, wherein the semiconductor memory device isa stacked memory device in which a plurality of chips communicating dataand control signals through a through-silicon-via (TSV) are stacked. 9.The device according to claim 1, wherein the nonvolatile memory cellarray includes an anti-fuse cell array having a plurality of anti-fusecells.
 10. The device according to claim 1, wherein a number of bits ofthe first set of parity bits is smaller than a number of bits of theinput data.
 11. A semiconductor memory device, comprising: a dynamicrandom access memory (DRAM) cell array; a nonvolatile memory cell arrayconfigured to store input data and a first set of parity bits having atleast one bit, the input data and the first set of parity bits receivedfrom outside the semiconductor memory device; and an error correctioncircuit configured to generate second data as corrected data based onfirst data corresponding to the input data, the first data beingreceived from the nonvolatile memory cell array, and a second set ofparity bits corresponding to the first set of parity bits, the secondset of parity bits being received from the nonvolatile memory cellarray, wherein the semiconductor memory device is configured to use thesecond data to repair a defective cell included in the DRAM cell array.12. The device according to claim 11, wherein the semiconductor memorydevice is configured to use the second data as corrected data if thefirst data is different from the input data.
 13. The device according toclaim 11, wherein the semiconductor memory device is configured to usethe second data to replace a defective word line of the DRAM cell arraywith a spare word line.
 14. The device according to claim 11, whereinthe semiconductor memory device is configured to use the second data toreplace a defective column selecting line of the DRAM cell array with aspare column selecting line.
 15. The device according to claim 11,wherein the nonvolatile memory cell array includes an anti-fuse cellarray having a plurality of anti-fuse cells.
 16. A semiconductor memorydevice comprising: a memory cell array; a parity bit generatorconfigured to generate a first set of parity bits having at least onebit based on first data received from outside the semiconductor memorydevice; an anti-fuse cell array including a plurality of anti-fuse cellsconfigured to store the first data and the first set of parity bits, andto transfer second data corresponding to the first data, and a secondset of parity bits corresponding to the first set of parity bits; and anerror correction circuit configured to generate third data as correcteddata based on the second data and the second set of parity bits, whereinthe semiconductor memory device is configured to use the third data toselect a spare cell of the memory cell array.
 17. The semiconductormemory device of claim 16, wherein the memory cell array includes aplurality of dynamic random memory (DRAM) cells.
 18. The semiconductormemory device of claim 16, wherein a number of bits of the first set ofparity bits is smaller than a number of bits of the first data.
 19. Thesemiconductor memory device of claim 16, wherein the memory cell arrayincludes a normal memory cell array connected to word lines and columnselecting lines, and a spare memory cell array connected to one or morespare word lines and one or more spare column selecting lines, andwherein the third data is address information used to select at leastone of the spare word lines and the spare column selecting lines. 20.The semiconductor memory device of claim 19, further comprising a rowcomparator circuit configured to compare an input address to the thirddata, and a column comparator circuit configured to compare an inputaddress to the third data.